Embodiments of the present invention relate to microprocessors. More particularly, embodiments of the present invention relate to an expanded set of registers in a microprocessor.
A known microprocessor architecture is the IA-32 architecture of Intel Corp. of Santa Clara, Calif. The IA-32 architecture includes 32-bit general integer registers. The general integer registers can be used as operands for calculations and for addressing. For example, a register can store a value that is part of an operation (e.g., an arithmetic operation, a logical operation, etc.). In another example, a register can store information relating to a memory address that stores a value that is part of an operation. The IA-32 architecture includes a small number of logical general integer registers, i.e., eight logical general integer registers. In general, fewer logical registers can disadvantageously effect system performance because software compilers can be limited in terms of optimizations that can be implemented. For example, fewer registers can require increased accesses to memory and/or stack, which can decrease system performance. In view of the foregoing, it can be appreciated that a substantial need exists for methods and apparatus which can advantageously support an expanded logical register set.